1. Field of the Invention
This invention relates to a data processing device and more particularly to a data processing device having a memory which permits writing and reading of digital data into and from the memory.
2. Description of the Related Art
As a result of the recent increase in capacity and reduction in size of memory devices, memory devices capable of storing one frame portion of a TV signal, such as the one called a frame memory, have come to be used for apparatuses designed for the general public users. The use of such memory devices, for example, for still-picture or slow-motion reproduction or the like has come to enable a VTR to give non-standard reproduced pictures with high quality.
Meanwhile, a system for digitally recording a still picture with a VTR, separately from an analog video signal, by using the memory of the above stated kind has been proposed, as disclosed in U.S. patent application Ser. No. 937,872. This system enables even the VTR of the kind called a home VTR to record and reproduce a still picture of very high quality.
FIG. 1 of the accompanying drawings shows the simplest arrangement for writing and reading a video signal into and from the frame memory. The illustration includes an input terminal 1 arranged to receive an analog video signal; and an analog-to-digital (hereinafter referred to as A/D) converter 2. A digital signal on line 3 which is produced from the A/D converter 2 is written into or read out from a memory 4 in accordance with an address obtained from an address generator 8 over lines 9. A digital signal on line 5 read out from the memory 4 is converted back to an analog signal by a digital-to-analog (hereinafter referred to as D/A) converter 6. The analog signal thus obtained is produced from an output terminal 7.
FIGS. 2(a) to 2(d) show in a timing writing and reading actions performed on this memory 4. The writing and reading actions on the memory 4 are performed in a time sharing manner. Within a period during which the address generator 8 is designating one and the same address, the reading action is performed during the first half of the period and the writing action during the latter half period. Change-over from reading to writing is accomplished in accordance with a writing control signal which is given from the address generator 8 to the memory 4 as shown in FIG. 2(d).
In the timing chart, FIG. 2(a) shows addresses given from the address generator 8. FIG. 2(b) shows the digital produced from the memory 4. FIG. 2(c) shows the digital signal supplied to the memory 4. FIG. 2(d) shows the writing control signal. This timing chart is on the assumption that the cycle time T of the writing and reading actions on the memory 4 is the same as the sampling period of the A/D converter 2. If the operation of the memory 4 is slow and the above stated cycle time thus must be set at a value longer than the sampling period, the cycle time can be equivalently made to coincide with the sampling period by arranging a plurality of memories in parallel and by using them as one memory.
The digital signal produced from the memory 4 is somewhat behind the designated timing of the address. This delay is caused by an access time resulting from the structural characteristic of the memory. Once a writing action is performed after the output timing of the memory 4 is set, the output timing is unvarying. In actual arrangement, therefore, a latch circuit is provided at the output terminal of the memory 4. The output of the memory 4 is supplied to the D/A converter 6 after the output is held by the latch circuit.
The contents of the memory are incessantly renewed as long as the memory 4 is in operation. However, it is possible to retain the contents of the memory 4 by inhibiting a writing action by keeping at a low level the writing control signal which is as shown in FIG. 2(d). For example, it is possible to obtain a still picture from the memory 4 even when a motion picture signal is received at the input terminal 1.
FIG. 3 shows another example of the conventional arrangement for writing and reading a video signal into and from the frame memory. In FIG. 3, the same components as those shown in FIG. 1 are indicated by the same reference numerals and the details of them are omitted from this description. In the case of this arrangement, the digital signal from the A/D converter 2 is written into the memory 4 in accordance with an address obtained from a writing address generator 10. The digital signal from the memory 4 is read out and supplied to the D/A converter 6 in accordance with an address obtained from a reading address generator 11. There is provided a manual operation part for designating a reading address. This arrangement makes it possible to differentiate a writing address from a reading address. This enables a picture to be enlarged, reduced, inverted or processed to give some other special effect. Further, the transmission rate of the incoming digital signal and that of the outgoing digital signal can be arranged to differ from each other without difficulty.
FIGS. 4(a) to 4(d) show in a timing chart the operation of the memory of FIG. 3. FIG. 4(a) shows writing (W) and reading (R) addresses. FIGS. 4(b), 4(c) and 4(d) show the same things as FIGS. 2(b), 2(c) and 2(d). In this case, the reading cycle TRC and the writing cycle TWC are arranged to be normally the same. Therefore, the sample period of the A/D converter 2 can be expressed as TRC +TWC. The memory 4 of FIG. 3 thus must be operated at a speed twice as high as the operation of the memory 4 of FIG. 1. The memory, therefore, must be capable of operating at a high speed.
FIG. 5 shows by way of example a system for recording and reproducing a still picture on and from a tape by using a memory of the above stated kind and by utilizing the recording and reproducing functions of a VTR disclosed in the previous patent application cited in the foregoing. An NTSC standard camera 110 is arranged to be driven at a rate of 525 lines/frame, 60 field/sec and 30 frames/sec on the basis of a synchronizing (hereinafter referred to as sync) signal which will be described later herein. A video signal produced from the camera 110 is serially supplied to an A/D converter 112. The A/D converter 112 samples the input signal at a sampling frequency fs which satisfies the Nyquist theorem. The sampled signal is quantized (in 8 bits, for example). The quantized output of the A/D converter 112 is written in at a corresponding address of a memory 114. The data written in the memory 114 is read out and supplied to a D/A converter 116 to be converted into an analog signal as necessary. The output terminal of the D/A converter 116 is connected to an NTSC standard monitor 118.
A circuit which forms the sync signal for driving the standard camera 110 and various clock pulses is arranged as follows: An original oscillator 120 is arranged to generate reference clock signal, which is applied to a frequency dividing circuit 122 and a memory control circuit 124. The memory control circuit 124 is arranged to prepare various clock signals on the basis of the reference clock signal for driving a memory 114. These various clock signals are supplied to the memory 114 along with an address signal. The frequency dividing circuit 122 is arranged to frequency divide the reference clock signal and supplies a frequency divided signal to a horizontal counter 126. The circuit 122 also supplies an A/D converter 112 and a D/A converter 116 with a sampling clock signal which is of a frequency fs. The horizontal counter 126 is arranged to prepare a horizontal sync signal HD of a frequency fH by counting the pulses of the clock signal received from the frequency dividing circuit 122. The counter 126 supplies a count value thus obtained to a ROM 128 and the horizontal sync signal HD to a vertical counter 130 respectively. The vertical counter 130 is arranged to count the horizontal sync signal HD and to supply a count value thus obtained to the ROM 128. The ROM 128 is arranged to prepare a composite sync signal of the NTSC system on the basis of the count values from the horizontal and vertical counters 126 and 130. The composite sync signal is applied to the standard camera 110. An interface 132 is arranged to relay digital data read out from the memory 114 to a VTR 134.
The operation of the memory 114 is as follows: The circuit arrangement shown in FIG. 5 has two operation modes including a motion picture output mode and a still picture output mode. Generally, it is impossible to select writing or reading into or out of a memory during a period of time (hereinafter referred to as a period TM) which is determined by the characteristic of the element employed as the memory. Assuming that the sampling period Ts (=1/fs) is more than twice as much as the period TM, writing into and reading from the memory can be performed i real time. However, in the case of a system whereby one frame portion of a picture is to be transmitted in 1/60 sec, the sampling time Ts is often shorter than the period TM and it is difficult to write and read in real time.
Generally, therefore, a memory which serves as a buffer is arranged on the input side of the memory 114. A given number (an i number) of data is taken into the buffer memory in real time. Data is written into a j number of memories (i .ltoreq.j) in parallel within a period not exceeding 1/2 of a period of time iTs required in taking the data in. Then, the data is read out within the remaining half of the period of time iTs. The data thus read out is processed to be brought back to its original rate of transmission by means of a buffer memory. Such arrangement gives a period of iTs/2 for each of the writing and reading actions on the memory. If TM&lt;ITs/2, data writing and data reading thus can be accomplished apparently in a continuously manner. The period of time available for writing and reading into and out of the memory, i.e. the cycle time of the memory is as indicated by a reference symbol T1 in FIGS. 6(a) and 6(b) which shows the memory operation in a timing chart. Generally, this cycle time is set at a value which gives a sufficiently long allowance relative to the period TM. In the case of FIGS. 6(a) and 6(b), this cycle time is set at 1/8 of a horizontal scanning period excluding a horizontal blanking period BL. As a result, the memory 114 of FIG. 5 is arranged to write and read 1/4 of one horizontal scanning line portion of the NTSC signal at a time. In the motion picture output mode, the memory 114 repeats writing (W) and reading (R) in this manner at the timing as shown in FIG. 6(a). A video signal produced from the camera 110 is thus serially applied to a monitor 118. The monitor 118 then displays pictures taken by the camera 110 one after another.
In the still picture output mode, writing into the memory 114 is inhibited when one frame portion of the video signal is written into the memory 114. Then, as shown in FIG. 6(b), one frame portion of the video signal is recurrently read out from the memory 114 to have a still picture displayed by the monitor 118. In recording a still picture, during a horizontal blanking period BL as shown in FIGS. 6(a) and 6(b), the data of one horizontal scanning part stored by the memory 114 is transferred to the interface 132 to be digitally recorded by the VTR 134. The digital recording by the VTR 134 is as briefly described below:
Assuming that 4 N bytes of information is written in the memory 114 per horizontal scanning period (hereinafter referred to as a period H), the interface 132 receives 4 N bytes of information within one horizontal blanking period BL. Then, assuming that this VTR is of known 8 mm VTR standard specifications, the VTR is incapable of processing more than 4 bytes of information per period H. Therefore, the interface 132 is arranged to take in at a rate of one H portion of data in N number of periods H and to change its transmission rate to a given transmission rate in sending the data to the VTR 134 in the form of serial data. In this VTR, a PCM signal processing circuit is arranged in a well known manner and is, therefore, omitted from description here.
As described in the foregoing, the conventional system is arranged to have one and the same kind of video signal obtained, for example, by an NTSC standard camera displayed by an NTSC monitor and to have it PCM recorded by an 8 mm VTR. Meanwhile, however, a high definition type camera arranged as an image input device to operate at a rate of 1,051 lines/frame, 30 field/sec and 15 frames/sec has appeared during recent years. Further, a double scanning type monitor arranged as an image output device to operate at a rate of 525 lines/field, 60 fields/sec and 60 frames/sec has been developed. The conventional still picture recording/reproducing system described in the foregoing is hardly applicable to such a high definition camera and such a double scanning type monitor.